Standard Cell Design Lead

Substrate is addressing one of the most important technological problems facing the United States. At the intersection of advanced manufacturing and cutting-edge physics, we are developing technologies that will reshape the semiconductor industry and strengthen America's technological leadership. We are a team of world-class scientists, engineers, and technical experts building technology for the United States.

Summary

As a Standard Cell Design Lead, you will develop and optimize standard cell libraries while leading cell characterization and library validation efforts. This role requires deep expertise in digital cell design, layout, and timing characterization combined with strong understanding of library requirements for digital design flows. You will work across multiple locations including external fabrication facilities. This is a full-time, onsite position.

Responsibilities

Lead standard cell library development including logic gates, flip-flops, and complex cells

Optimize cell layouts for power, performance and area across Vth’s and drive strengths

Characterize cell library including timing, power, and noise analysis for library models

Develop Liberty (.lib) timing files and LEF physical abstractions for EDA tool integration

Collaborate with PDK and process teams to ensure cell performance meets targets

Implement DFM techniques and validate cells against DRC/LVS rules

Support all DFT fault models including cell aware, physical aware, stuck-at and transition

Optimize cell architectural requirements including multi-Vt and multi-channel options

Lead library validation and qualification across distributed design and fabrication teams

Required Qualifications

10+ years experience in standard cell design, library development and characterization

Deep understanding of standard cell architecture, layout, and optimization strategies

Strong background in cell characterization and Liberty timing model generation

Experience with layout tools (Cadence Virtuoso, Synopsys Custom Compiler, or similar)

Proficiency with characterization tools and SPICE simulation for timing/power analysis

Proven ability to balance area, performance, and power trade-offs in cell design

Preferred Qualifications

Advanced degree in Electrical Engineering or related field

Experience with advanced node standard cells or FinFET/GAA library development

Background in low-power design techniques and multi-threshold voltage libraries

Familiarity with EDA flows and library integration requirements

Experience in research-driven or startup semiconductor environments

Salary Range

$150,000-$275,000 USD

Substrate is an equal opportunity employer. It provides equal employment opportunity to all applicants without regard to race, color, religion, national origin, disability, medical condition, marital status, sex, gender, age, military or veteran status, or any other characteristic protected by applicable federal, state, or local laws.

Substrate will provide reasonable accommodations to applicants with disabilities. If you need an accommodation during the hiring process, please let your recruiter know.

Applicants must be legally authorized to work in the United States. This position is not eligible for visa sponsorship.