# Senior Verification Engineer at Accelercomm

> Hybrid · United States · Senior · Software engineering · open. Source: https://alderhq.app/jobs/pinpoint%3Aaccelercomm%3A591498 (read 2026-11-04).

## Facts (observed)

- Company: [Accelercomm](https://alderhq.app/companies/accelercomm)
- Location text: West Coast, United States
- Where it can be done from (inferred): Hybrid · United States (evidence: "Location: West Coast, United States")
- Posted: already open when tracking began; date unknown
- First seen by alder: 2026-11-04 · last verified: 2026-11-04
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://accelercomm.pinpointhq.com/en/postings/f703e7f2-f266-4476-a89f-986f636cd53a
- Skills listed (inferred): Python

## Pay and sponsorship

- Posted pay: not posted
- Market band for similar posted roles (United States, n 3519): p25 $160k, median $183k, p75 $210k

## Description (the employer's text)

Our RTL team delivers efficient ASIC and FPGA implementations of advanced communications algorithms, working across IP development, integration and verification. To support this work, we are looking for a Senior Verification Engineer to support the complete UVM verification of Accelercomm IP.

### Responsibilities

Responsible for verification of RTL implementations for advanced wireless communications IP and modem subsystems, ensuring designs meet functional, performance and quality requirements prior to FPGA deployment and ASIC tape-out.

- Develop verification plans from design and architecture specifications.
- Create and maintain SystemVerilog/UVM verification environments.
- Develop testbenches, assertions, scoreboards and coverage models.
- Execute directed and constrained-random verification.
- Analyse coverage and debug RTL and verification issues.
- Support subsystem and system-level integration activities.
- Contribute to automation, regression and CI workflows.
- Participate in design reviews and verification sign-off.
- Mentor and support junior colleagues
### Skills

Required

- Degree in Electronic Engineering, Computer Engineering or a related discipline.
- At least 3 years experience verifying digital ASIC and/or FPGA designs.
- Strong SystemVerilog and UVM skills.
- Understanding of RTL design principles and hardware implementation.
- Experience with coverage-driven and assertion-based verification.
- Linux proficiency and scripting skills (Python, Tcl or Bash).
- Strong analytical, debugging and problem-solving skills.
- Experience using AI to accelerate verification without sacrificing quality
- Ability to work across multiple teams
Desirable

- Experience in 4G/5G, NTN, satellite communications or DSP systems.
- Knowledge of modem architectures and Layer 1 processing.
- Experience with Formal Verification, FPGA prototyping and CI environments.
- Familiarity with MATLAB or equivalent modelling tools.
### Benefits

We offer a bonus scheme which pays up to 20% of salary annually, depending on performance. This is in addition to stock options and a range of good quality company benefits including 401K, health/dental/optical insurance. We operate flexible working hours and offer hybrid working.

Applicants with existing H-1B visa or practical training work authorization are welcome to apply if they are seeking a change of employer. We are unable to sponsor new applications

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Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/pinpoint%3Aaccelercomm%3A591498 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.