# Senior Design Engineer at Accelercomm > Hybrid · United Kingdom · Senior · Software engineering · open. Source: https://alderhq.app/jobs/pinpoint%3Aaccelercomm%3A579685 (read 2026-11-04). ## Facts (observed) - Company: [Accelercomm](https://alderhq.app/companies/accelercomm) - Location text: Cambridge, UK, Cambs - Where it can be done from (inferred): Hybrid · United Kingdom (evidence: "Location: Cambridge, UK, Cambs") - Posted: already open when tracking began; date unknown - First seen by alder: 2026-11-04 · last verified: 2026-11-04 - Reposted: 0 times · edited: 0 times - Apply on the employer's site: https://accelercomm.pinpointhq.com/en/postings/f39ed2a0-bfcd-4a79-b2a8-ac93eb8128c0 - Skills listed (inferred): Python, C++ ## Pay and sponsorship - Posted pay: not posted - Market band for similar posted roles (United Kingdom, n 43): p25 £81k, median £103k, p75 £134k ## Description (the employer's text) We are looking for multiple Senior Design Engineers who will work on revolutionary technology that is at the leading edge of non-terrestrial communications, a 5G base station to be deployed on board satellites. This technology will underpin the next generation of mobile standards, giving complete coverage to the entire globe. AccelerComm develops the baseband signal processing technology, using hardware acceleration to generate world-leading error resilience, capacity and power efficiency. You will work on the latest generation space-qualified devices, delivering standalone IP and integrated IP solutions. This is a Cambridge based role; please also take a look at our vacancies in Southampton and Bristol. ### Responsibilities - Work closely with the Algorithm and System Architecture teams to understand requirements and translate them into mirco-architectures for RTL implementations - Implement designs targeting both FPGA and ASIC using industry standard techniques, including the creation of appropriate testbenches - Deploy your designs onto the latest FPGA development platforms for validation and system integration - Actively engage with and adhere to AccelerComm engineering methodology, processes and design techniques, being able to offer improvements to efficiency and quality for both the design flow and the final product - Collaborate with colleagues across the whole design flow: micro-architecture, design, verification, physical implementation and optimisation for ASIC and FPGA ### Skills Essential: Expert knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products - A strong skillset in delivering digital designs in the ASIC and FPGA industry - Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis - Track record in collaborating across teams to produce integrated solutions - Experience in technical documentation writing – design specifications, user guides, verification plans - Expert user of EDA tools for simulation and synthesis Desirable: - Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming) - Familiarity with the AMBA bus protocols - Understanding of UVM verification techniques or practical experience using UVM for IP verification - Experience using C++/SystemC for design modelling and integration - Experience with high speed interfaces such as PCI-E or JESD - Knowledge of a scripting language, such as Python - Knowledge and appreciation of project methodologies across the design lifecycle, including agile and waterfall, requirement capture and traceability - Experience with AMD FPGAs and the associated design tools or with any EDA’s ASIC backend tools ### Benefits We pay competitive salaries which depend on skills and experience. We offer a bonus scheme which pays up to 20% of salary annually, depending on performance. This is in addition to EMI share options, issued periodically. We offer a range of good quality company benefits including pension and private health insurance. We operate flexible working hours and offer hybrid working. --- Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/pinpoint%3Aaccelercomm%3A579685 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.