# Senior Analog IC Layout Engineer at Semron

> Germany · Senior · Software engineering · open. Source: https://alderhq.app/jobs/personio%3Asemron%3A2862825 (read 2026-11-10).

## Facts (observed)

- Company: [Semron](https://alderhq.app/companies/semron)
- Location text: Dresden, DE (primary site)
- Where it can be done from (inferred): Germany (evidence: "Location: Dresden, DE (primary site)")
- Posted: 2026-10-27 (14 days ago)
- First seen by alder: 2026-11-07 · last verified: 2026-11-07
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://semron.jobs.personio.de/job/2862825
- Skills listed (inferred): Python

## Pay and sponsorship

- Posted pay: not posted
- Market band for similar posted roles (United States, n 3913): p25 $160k, median $183k, p75 $210k

## Description (the employer's text)

### About the Role

Location: Dresden, Germany (On-site)

### What you will do:

- Implement and optimize precision analog and mixed-signal layouts, applying advanced matching techniques such as interdigitation, common-centroid placement, symmetry, shielding, and guard rings.
- Perform full-chip integration, including block placement, I/O ring implementation, power distribution networks, and global/local signal routing using routing conduits and structured routing methodologies.
- Optimize layouts for matching, parasitic effects, noise isolation, signal integrity, and power distribution.
- Perform physical verification, including Design Rule Checking (DRC), Layout Versus Schematic (LVS), Electrical Rule Checking (ERC), electromigration (EM), and IR-drop analysis, and resolve identified violations.
- Collaborate with analog and digital design engineers on floorplanning, layout constraints, and integration requirements.
- Support parasitic extraction, post-layout verification, and final layout sign-off for tape-out.
### What you should bring in:

- Bachelor's degree in Electrical Engineering, Microelectronics, or a related field, or equivalent relevant industry experience.
- Minimum 5 years of hands-on experience in analog or mixed-signal IC layout design.
- Strong understanding of CMOS layout principles, semiconductor process technologies, and layout-dependent effects.
- Proficiency with Cadence Virtuoso or Synopsys Custom Compiler.
- Experience with industry-standard physical verification tools and flows for DRC, LVS, DFM and parasitic extraction.
- Demonstrated experience with chip-level integration, floorplanning, I/O rings, power distribution, and hierarchical routing.
- Experience taking IC layouts through physical verification and tape-out
- Experience with advanced CMOS process technologies, including FD-SOI, high-voltage BCD and multi-layer interconnect structures.
- Strong system-level mindset.
- Effective team communication.
### Helpful but not required:

- Experience with large-scale mixed-signal chip integration and complex power distribution networks.
- Experience with FinFET technologies.
- Experience with layout automation, scripting, or productivity tools such as SKILL, Tcl, or Python.
### Why us?

We offer the opportunity to develop innovative AI hardware accelerator based on SEMRON's proprietary CapRAM technology in a dynamic startup environment with challenging technical problems, opportunities for professional growth and close collaboration with a multidisciplinary team across analog, digital and device engineering teams. You will have significant technical ownership of analog layout and chip-level physical integration.

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Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/personio%3Asemron%3A2862825 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.