# Senior Analog IC Design Engineer at Semron

> Germany · Senior · Software engineering · open. Source: https://alderhq.app/jobs/personio%3Asemron%3A1369490 (read 2026-11-10).

## Facts (observed)

- Company: [Semron](https://alderhq.app/companies/semron)
- Location text: Dresden, DE (primary site); Austin, TX
- Where it can be done from (inferred): Germany (evidence: "Location: Dresden, DE (primary site); Austin, TX")
- Posted: 2023-12-24 (1051 days ago)
- First seen by alder: 2026-11-07 · last verified: 2026-11-07
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://semron.jobs.personio.de/job/1369490
- Skills listed (inferred): Python

## Pay and sponsorship

- Posted pay: not posted
- Market band for similar posted roles (Austin, n 41): p25 $158k, median $181k, p75 $214k

## Description (the employer's text)

### About the Role

You will take ownership of critical circuit blocks from specification through silicon implementation, working closely with system architects, device engineers, digital designers, and layout engineers.

Locations:

Dresden, Germany (On-site)

Austin, USA (On-site)

### What you will do:

- Design and optimize transistor-level analog and mixed-signal circuits for CapRAM-based in-memory computing architectures, with a focus on power, performance, area, and precision.
- Develop precision analog building blocks, including amplifiers, comparators, biasing circuits, voltage and current references, and charge-domain circuits.
- Design ultra-low-power ADCs, memory-array peripheral circuits, and sensing and readout interfaces.
- Design and optimize power-management, supply-conditioning, and high-voltage programming circuits.
- Perform comprehensive circuit analysis and verification, including stability, noise, PVT, Monte Carlo, and post-layout simulations.
- Collaborate with system architects and device engineers to translate system requirements into circuit specifications and implementations.
- Work closely with layout engineers to ensure robust physical implementations, addressing matching, parasitics, and signal integrity.
- Support silicon bring-up, characterization, debugging, and the development of reusable analog IP.
### What you should bring in:

- Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or a related field.
- Minimum 5 years of hands-on industry experience in analog or mixed-signal CMOS IC design.
- Strong understanding of semiconductor device physics, transistor-level circuit operation, and analog design trade-offs.
- Solid foundation in feedback theory, small-signal AC analysis, frequency response, loop stability, compensation techniques, gain and phase margins, and settling behavior.
- Strong understanding of precision and ultra-low-power circuit techniques, including noise, mismatch, offset, linearity, and low-voltage design.
- Knowledge of capacitive and switched-capacitor circuit techniques, including charge redistribution, charge injection, leakage, and parasitic effects.
- Proficiency with EDA tools and industry-standard analog design and verification methodologies.
- Experience with at least one complete IC development cycle, including tape-out.
- Strong system-level mindset.
- Effective team communication.
### Helpful but not required:

- Experience with SAR ADCs, charge-redistribution ADCs, dynamic comparators, and advanced low-power amplifier techniques.
- Experience with analog in-memory computing, emerging memory technologies, or capacitive sensing and readout circuits.
- Familiarity with high-voltage programming techniques, level shifting, LDOs, and power-supply design.
- Understanding of analog circuit nonidealities and their impact on system-level computational accuracy.
- Experience with silicon characterization, debugging, and behavioral modeling using Verilog-A, MATLAB, or Python.
- Experience working in a semiconductor startup or an early-stage technology development environment
### Why us?

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Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/personio%3Asemron%3A1369490 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.