# CPU Physical Design Engineer - Full Time at RosaicLabs

> Hybrid · United States · Unspecified · Software engineering · open. Source: https://alderhq.app/jobs/lever%3Arosaiclabs%3Ade541731-dbe2-409a-bfa3-a4e68e933db0 (read 2026-11-04).

## Facts (observed)

- Company: [RosaicLabs](https://alderhq.app/companies/rosaiclabs)
- Location text: Santa Clara, CA; Austin, TX
- Where it can be done from (inferred): Hybrid · United States (evidence: "Location: Santa Clara, CA; Austin, TX")
- Posted: 2026-10-05 (30 days ago)
- First seen by alder: 2026-11-02 · last verified: 2026-11-04
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://jobs.lever.co/rosaiclabs/de541731-dbe2-409a-bfa3-a4e68e933db0
- Skills listed (inferred): Python

## Pay and sponsorship

- Posted pay: $125k–$250k per year (from the listing's pay field)
- Market band for similar posted roles (SF Bay Area, n 1495): p25 $161k, median $200k, p75 $247k
- H-1B filings at this company for similar roles, FY26: 2 ([US DOL OFLC LCA disclosure data](https://www.dol.gov/agencies/eta/foreign-labor/performance))

## Description (the employer's text)

### What you'll do

Analyze CPU microarchitecture (pipeline stages, execution units, cache hierarchy, branch prediction) to guide implementation tradeoffs on timing, power, and area

Develop and own gate-level design for CPU blocks: standard-cell selection, logic restructuring, and clock-domain/reset architecture

Perform transistor-level design and custom circuit work for critical-path structures (register files, custom datapaths, memory arrays, high-speed logic)

Drive logic synthesis, floorplanning, power planning, placement, clock-tree synthesis (CTS), and routing to closure

Own static timing analysis (STA), signal integrity, IR drop/electromigration analysis, and physical/electrical signoff

Debug and close timing, power, and DRC/LVS violations across corners and modes

Collaborate with RTL design, DFT, verification, and package/system teams to co-optimize PPA (power, performance, area)

Develop and improve physical design flows, scripts, and methodologies to boost QoR and turnaround time

Participate in design reviews, correlate silicon results with pre-silicon predictions, and drive root-cause debug of PPA gaps

### What we're looking for

Master's degree in Electrical Engineering, Computer Engineering, or a related field

5+ years of industry experience in CPU or high-performance ASIC physical design

Strong understanding of CPU microarchitecture: pipelines, out-of-order execution, caches, branch prediction, and interconnect

Hands-on experience with gate-level design, including standard-cell logic design and clock/reset architecture

Working knowledge of transistor-level/custom circuit design for high-speed and low-power structures

Proven track record driving synthesis and place-and-route (P&R) to timing, power, and area closure on complex blocks

Solid grasp of static timing analysis (STA), signal integrity, and physical verification (DRC/LVS)

Proficiency with industry-standard EDA tools for synthesis, P&R, and signoff (see Tools & Technologies)

Scripting proficiency in Tcl, Perl, or Python for flow automation

Strong analytical and debugging skills, with the ability to work through cross-corner, cross-mode PPA tradeoffs

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Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/lever%3Arosaiclabs%3Ade541731-dbe2-409a-bfa3-a4e68e933db0 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.