# CPU Fabric and Interconnect Verification Engineer at NUVACORE

> Hybrid · India · Unspecified · Software engineering · open. Source: https://alderhq.app/jobs/lever%3Anuvacore%3A1cdd8251-2c6e-4aa1-b2cf-10fcc3f7fe2e (read 2026-11-06).

## Facts (observed)

- Company: [NUVACORE](https://alderhq.app/companies/nuvacore)
- Location text: Bangalore; Austin, TX; Santa Clara, CA
- Where it can be done from (inferred): Hybrid · India (evidence: "Location lists "bangalore"")
- Posted: 2026-09-18 (49 days ago)
- First seen by alder: 2026-11-02 · last verified: 2026-11-04
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://jobs.lever.co/nuvacore/1cdd8251-2c6e-4aa1-b2cf-10fcc3f7fe2e
- Skills listed (inferred): Python, C++

## Pay and sponsorship

- Posted pay: $140k–$250k per year (from the listing's pay field)
- Market band for similar posted roles (Bengaluru, n 3): p25 $125k, median $159k, p75 $177k
- H-1B filings at this company for similar roles, FY26: 7, median offered wage $183k ([US DOL OFLC LCA disclosure data](https://www.dol.gov/agencies/eta/foreign-labor/performance))

## Description (the employer's text)

At NUVACORE we're designing a new general-purpose CPU core for the sustained, intensive demands of AI infrastructure and agentic computing, not the workloads of the past. We are seeking Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove the correctness of the Nuvacore interconnect fabric. As part of the design verification (DV) team, you will help verify the coherent and non-coherent interconnect — building the test plans, environments, and checkers that find deep bugs in transport, ordering, and coherence long before silicon, working shoulder-to-shoulder with architecture and RTL design.

THE ROLE

Plan & Strategy: Drive the verification scope, strategy, and test plans for the interconnect fabric — coherent and non-coherent, including crossbars, routing, and bus interfaces.

Environment Setup: Build, maintain, and scale robust verification environments — stimulus generators, protocol checkers, transactors, and coverage — that exercise coherent and non-coherent transactions end to end.

Test & Debug: Generate directed and random traffic to expose corner cases such as ordering, arbitration, QoS, and deadlock/livelock avoidance.

Performance Verification: Partner with architects to correlate RTL against performance models, hunting bandwidth, latency, and QoS issues.

Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the test plan is complete.

Cross-functional Collaboration: Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support emulation, FPGA, and silicon bring-up.

REQUIREMENTS — MUST HAVE

Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.

15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.

Strong knowledge of interconnect/fabric architecture and digital logic — coherent and non-coherent protocols (e.g. AMBA, CHI, TileLink) and on-chip transport.

Hands-on functional verification: test plans, testbenches, protocol checkers, transactors, and coverage.

Proficiency in C/C++ and/or SystemVerilog, plus a scripting language (Python; Perl a plus).

Experience writing and debugging tests for complex digital designs.

REQUIREMENTS — NICE TO HAVE

Interconnect, network-on-chip (NoC), or fabric verification.

Coherent and non-coherent bus-protocol verification.

Protocol checkers and formal verification (deadlock/livelock, protocol compliance).

Constrained-random verification and coverage-driven closure.

Performance and QoS verification of interconnect.

Emulation/FPGA and silicon bring-up and debug (waveforms, trace).

The next great CPU won't build itself. We’re assembling a world-class team across every layer of CPU development, from architecture and design to verification, physical implementation, software, infrastructure, and product delivery. Every discipline matters, and every person has the opportunity to help shape the technology from the ground up.

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Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/lever%3Anuvacore%3A1cdd8251-2c6e-4aa1-b2cf-10fcc3f7fe2e and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.