# DV - Staff (+) Verification Engineer - AMS modeling at Eliyan

> Onsite · United States · Staff · Software engineering · open. Source: https://alderhq.app/jobs/lever%3Aeliyan%3Adfb7db8a-4849-4e1b-b44e-f2ffa603f3ce (read 2026-11-05).

## Facts (observed)

- Company: [Eliyan](https://alderhq.app/companies/eliyan)
- Location text: Bay Area, Vancouver or Toronto
- Where it can be done from (inferred): Onsite · United States (evidence: "Location: Bay Area, Vancouver or Toronto")
- Posted: 2026-05-20 (168 days ago)
- First seen by alder: 2026-11-02 · last verified: 2026-11-04
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://jobs.lever.co/eliyan/dfb7db8a-4849-4e1b-b44e-f2ffa603f3ce
- Skills listed (inferred): Python

## Pay and sponsorship

- Posted pay: not posted
- Market band for similar posted roles (SF Bay Area, n 851): p25 $206k, median $240k, p75 $281k
- H-1B filings at this company for similar roles, FY26: 3, median offered wage $200k ([US DOL OFLC LCA disclosure data](https://www.dol.gov/agencies/eta/foreign-labor/performance))

## Description (the employer's text)

Join the leading chiplet startup! As an Eliyan Verification Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. In this role you will lead the verification of Serdes. You will be developing state-of-the-art AMS systemVerilog models (RNM) for best-in-class PHYs. You will own verification of AMS SystemVerilog models. This is a hands-on technical role. You'll work with analog team, look at schematics and write the RNM models. We offer a fun work environment with excellent benefits. We offer a fun work environment with excellent benefits. ONSITE M-F.

### Key Responsibilities:

- Develop and execute RNM AMS model for best in class PHYs.
- Make sure the quality of models reflects schemetics.
- Write and debug SystemVerilog/UVM compliant test cases
- Collaborate with design team to ensure design quality
- Expertise to understand analog blocks.
### Required Qualifications:

- 5+yrs relevant experience
- BS in EE or related field.
- Deep analog design expertise
- Knowledge of SystemVerilog, test environment and assertion coding
- Experience in verifying mixed signal IPs
### Preferred Qualifications:

- Experience with Formal verification with Jasper Gold or vc-formal
- Python/Perl/Tcl scripting for design verification

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Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/lever%3Aeliyan%3Adfb7db8a-4849-4e1b-b44e-f2ffa603f3ce and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.