About SiTime

SiTime is the Precision Timing company.

Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com.

Job Summary

SiTime is seeking a seasoned Principal DFT Engineer to lead the DFT architecture, implementation, verification, and signoff of complex digital blocks and subsystems. The successful candidate will take end-to-end ownership of DFT from architecture and specification through implementation, coverage closure, silicon bring-up, and manufacturing support. This role serves as a technical leader for DFT, shaping methodology and automation, resolving complex cross-functional challenges, and establishing engineering best practices across multiple programs. We value diverse experiences, perspectives, and career paths, and welcome candidates who are excited to contribute to our mission.

Responsibilities

Serve as the technical focal point for DFT, leading architecture, implementation, verification, and signoff reviews, and establishing reusable methodologies across multiple programs.
Define DFT architecture and specifications, including scan architecture, compression, test access, clocking, test modes, core wrapping, and hierarchical DFT strategy.
Implement and validate digital DFT structures, including scan insertion, OCC insertion, advanced compression architectures such as EDT and LPCT, and core wrapping.
Develop and continuously improve automated, reproducible DFT implementation, verification, ATPG, and signoff flows to increase productivity, reduce execution risk, and ensure consistent test quality across multiple programs.
Own ATPG generation, pattern validation, fault analysis, and coverage closure, identifying and resolving testability limitations to achieve product coverage and quality targets.
Define, develop, and verify timing constraints for functional, scan-shift, capture, and other test modes.
Collaborate closely with RTL and Physical Design teams to identify and resolve testability issues early in the design cycle, meet coverage requirements, and integrate DFT implementations.
Partner with ATE and product/test engineering teams to bring up test patterns on silicon, diagnose pattern and test failures, support yield learning, and drive issues to closure.
It is not necessary to meet all job requirements to be a qualified candidate for the position.

Qualifications & Requirements

MS. in Electrical Engineering, Computer Engineering, or a related field with a minimum of 10 years of relevant experience, or a Ph.D. with a minimum of 6 years of relevant experience.
Hands-on experience driving DFT implementation and signoff through successful tape-outs on advanced process nodes.
Deep hands-on experience with industry-standard DFT insertion, ATPG, and verification tools (e.g., Siemens Tessent, Synopsys TestMAX, or Cadence Modus).
Strong scripting capability in Tcl, Perl, and/or Python, applied to DFT flow automation, test pattern generation, and custom reporting.
Strong understanding of SDC timing constraints for functional, scan-shift, and capture modes, and their interaction with multi-mode, multi-corner timing closure
Thorough knowledge of static DFT analysis, fault modeling, ATPG pattern generation, and gate-level simulation (GLS) with timing.
Experience driving DFT-related timing and implementation closure in collaboration with Physical Design, including scan-chain, test-clock, test-mode, and ECO-related issues through signoff.