# ASIC Engineer at Jane Street

> United States · Unspecified · Software engineering · open. Source: https://alderhq.app/jobs/greenhouse%3Ajanestreet%3A8213653002 (read 2026-11-14).

## Facts (observed)

- Company: [Jane Street](https://alderhq.app/companies/jane-street)
- Location text: New York, New York, United States; New York
- Where it can be done from (inferred): United States (evidence: "Location: New York, New York, United States; New York")
- Posted: 2025-10-29 (381 days ago)
- First seen by alder: 2026-11-02 · last verified: 2026-11-13
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://www.janestreet.com/join-jane-street/apply/8213653002?gh_jid=8213653002
- Skills listed (inferred): Python, Java, C++

## Pay and sponsorship

- Posted pay: not posted
- Market band for similar posted roles (New York, n 850): p25 $145k, median $180k, p75 $220k

## Description (the employer's text)

### About the Position

We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you’ll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. We are looking for someone who can contribute to all of our projects and be happy to work on both FPGA-based and ASIC-based technologies.

We’re big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That’s why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don’t expect you to know OCaml (we’ll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.

### About You

- 4+ years of practical experience in RTL design and verification, with a significant focus on ASIC design verification.
- Experience verifying ASIC designs using either Synopsys or Cadence tools.
- Experience applying software engineering techniques to improve the hardware design process and programming in high-level languages such as Python, C++, Java, or Haskell.
- Additional (preferred) experience in any of the following; formal verification, front-end RTL design and synthesis, or back-end physical design.
If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.

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Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/greenhouse%3Ajanestreet%3A8213653002 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.