# Principal Analog Design Engineer at Celero Communications, Inc

> United States · Principal · Software engineering · open. Source: https://alderhq.app/jobs/greenhouse%3Acelerocommunicationsinc%3A4157957009 (read 2026-11-15).

## Facts (observed)

- Company: [Celero Communications, Inc](https://alderhq.app/companies/celero-communications-inc)
- Location text: San Jose, CA; Irvine, CA; Ottawa, Canada; San Jose, CA; Vancouver, Canada
- Where it can be done from (inferred): United States (evidence: "Location: San Jose, CA; Irvine, CA; Ottawa, Canada; San Jose, CA; Vancouver, Canada")
- Posted: 2026-02-27 (261 days ago)
- First seen by alder: 2026-11-04 · last verified: 2026-11-10
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://job-boards.greenhouse.io/celerocommunicationsinc/jobs/4157957009

## Pay and sponsorship

- Posted pay: $150k–$250k per year (from the description)
- Market band for similar posted roles (SF Bay Area, n 214): p25 $225k, median $270k, p75 $320k

## Description (the employer's text)

Are you an Analog Design Engineer passionate about building the high-speed interconnect technology powering the next generation of AI? Join our fast-growing semiconductor startup and help develop disruptive mixed-signal solutions that enable tomorrow's AI infrastructure. We are seeking experienced Analog Design Engineers to architect, design, and deliver high-performance analog and mixed-signal circuits for next-generation transceivers and other critical high-speed functions. This is an opportunity to work alongside a world-class engineering team, tackle challenging design problems in advanced process technologies, and make a direct impact on innovative products from architecture through silicon.

Locations: Irvine, CA (HQ) \| San Jose, CA \| Vancouver, BC \| Ottawa, ON

### What You Will Do

• High speed analog circuit design, such as high-speed broadband amplifiers (VGA, CTLE, DRV, etc.)

• Clock generation and distribution (VCOs, PLL, clock distribution, etc.)

• Fundamental analog blocks (bandgap references, LDOs, temp sensors, etc.)

• New techniques for the development of next generation optical transceiver

• Design of custom passive components, from concept to silicon implementation

• Supervise analog layouts within advanced process nodes

• System verification and circuit design spec creation

• Silicon bring-up, debug and support

• Team communication and documentation

### What You Will Bring

• Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of experience

• Should have strong analog design fundamentals and experience in designing analog circuit blocks for broadband amplification, clock generation and distribution, and/or fundamental analog blocks

• Experience with analog design and verification tools (Virtuoso, Spectre, ADE, and post layout extraction tools) is a must

• Experience in advance CMOS design and verification flows (tools to evaluate self-heating, electromigration, safe operating area)

• Experience with electromagnetic simulation tools (EMX, Momentum, HFSS or other) is a plus

• Knowledge of the fundamentals on electromagnetism, lump models, and high frequency design

• Good understanding of analog layouts in FinFET and its effect on high-speed designs is a plus

• Strong communication and documentation skills

Annual Base Salary Range for US: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

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Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/greenhouse%3Acelerocommunicationsinc%3A4157957009 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.