# Design Verification Engineer at Baidu USA

> United States · Unspecified · Software engineering · open. Source: https://alderhq.app/jobs/greenhouse%3Abaidu%3A3234390 (read 2026-11-04).

## Facts (observed)

- Company: [Baidu USA](https://alderhq.app/companies/baidu-usa)
- Location text: Sunnyvale,CA; Sunnyvale, CA
- Where it can be done from (inferred): United States (evidence: "Location: Sunnyvale,CA; Sunnyvale, CA")
- Posted: 2021-06-18 (1966 days ago)
- First seen by alder: 2026-11-02 · last verified: 2026-11-04
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://job-boards.greenhouse.io/baidu/jobs/3234390
- Skills listed (inferred): Python, C++

## Pay and sponsorship

- Posted pay: not posted
- Market band for similar posted roles (SF Bay Area, n 1495): p25 $161k, median $200k, p75 $247k

## Description (the employer's text)

Do you want to be part of the AI revolution? Do you want to think out of the box, thriving on challenges in AI industry and have the desire to solve them? Do you want to work with a world-class team to explore the fast-growing AI hardware opportunities and impact on AI industry?

We’re looking forward to you joining us to collaborate, contribute, and revolutionize AI silicon and system.

### Description

We are looking for an experienced design verification engineer to join our SoC team at Baidu’s Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive in this highly technical environment. Your job responsibilities as a Design Verification Engineer will help the team to verify the functionality of Baidu's AI SoC at both block level and SoC level.

You will help on UVM Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development.

Run RTL and gate level functional verification, debug failures, lead bug tracking, and analyze and close coverage.

Work closely with the design and systems engineering teams to review specifications and architecture, extract features, define verification plan & coverage model.

Support mixed-signal co-simulation using Verilog models of analog IP. Develop testbench, test cases, reference model, coverage model and automation of regression suite.

Support emulation and silicon bring up debug with your smart ideas to duplicate the problem in simulation.

### Qualifications

- Minimum 5 years of experience of UVM based verification on a significantly complex project.
- Advanced knowledge of standard ASIC design and verification flows, simulation and testbench development.
- Advanced knowledge of System Verilog and the UVM methodology.
- Solid verification skills in problem solving, constrained random testing, coverage closure, gate level simulations, X propagation.
- Good practice of one scripting language (Perl, Python, Tcl) no preference.
- SoC and IP verification experience on either one aspect (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache).
- Familiar with C/C++.
- Formal Verification (Model Checking, Equivalence Checking).
- Excellent communication skills in both English and Chinese.
### Culture Fit

- Mission alignment: If you want to be part of a team to accomplish this great mission, we will provide you the best possible platform to do that.
- Self-directed: We work best with people that are driven, motivated, and aspire to greatness.
- Hungry to learn: We are eager to see you learn new skills and grow.
- Team orientation: We work in small, fast-moving teams. We watch out for each other and go after big goals together as a team.
#LI-DNI

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Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/greenhouse%3Abaidu%3A3234390 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.