# Low Power SoC Hardware Architect at Baidu USA

> United States · Staff · Other · open. Source: https://alderhq.app/jobs/greenhouse%3Abaidu%3A3234325 (read 2026-11-04).

## Facts (observed)

- Company: [Baidu USA](https://alderhq.app/companies/baidu-usa)
- Location text: Sunnyvale,CA; Sunnyvale, CA
- Where it can be done from (inferred): United States (evidence: "Location: Sunnyvale,CA; Sunnyvale, CA")
- Posted: 2021-06-18 (1965 days ago)
- First seen by alder: 2026-11-02 · last verified: 2026-11-04
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://job-boards.greenhouse.io/baidu/jobs/3234325
- Skills listed (inferred): Python, C++

## Pay and sponsorship

- Posted pay: not posted
- Market band for similar posted roles (SF Bay Area, n 631): p25 $180k, median $215k, p75 $252k
- H-1B filings at this company for similar roles, FY25: 2 ([US DOL OFLC LCA disclosure data](https://www.dol.gov/agencies/eta/foreign-labor/performance))

## Description (the employer's text)

Do you want to be part of the AI revolution? Do you want to think out of the box, thriving on challenges in AI industry and have the desire to solve them? Do you want to work with a world-class team to explore the fast-growing AI hardware opportunities and impact on AI industry?

We’re looking forward to you joining us to collaborate, contribute, and revolutionize AI silicon and system.

### Description

As a Low Power SoC Architect, you will have the opportunity to independently design and define the lower power subsystem and improve the power efficiency of AI engine, in both data center and edge SoC. You will collaborate with experienced designers, RTL engineers, system and software team, to explore feasibility of ideas, proof of concept and power performance improvement.

### Qualifications

- Experience and knowledge of lower power soc architecture and deep expertise in lower power subsystem, power efficient design.
- Lead and drive lower power & most efficient BW to power SoC design, including arch features, RTL changes for low power design, topologies with floorplan/layout and other design aspects
- Work with IPs architects to drive low power design, methodologies, techniques, and features.
- Drive SoC level power convergence by using existing modeling tools and techniques, and developing new state of the art tools, flows, and methodologies.
- Experience and proof of track in power optimization: perf@watt and perf/sq.mm modeling or analysis, is a plus
- Good teamwork with communications and support to solve all levels of architecture definition from micro-architecture to system level to software architecture.
- Proficiency in C/C++ and scripting languages such as Perl or Python.
- Self-driven and leadership skills.
- Knowledge or experience in automotive industry is a plus.
- MS or PhD in Electrical or Computer Engineering.
- Excellent communication skills in both English and Chinese.
### Culture Fit

- Mission alignment: If you want to be part of a team to accomplish this great mission, we will provide you the best possible platform to do that.
- Self-directed: We work best with people that are driven, motivated, and aspire to greatness.
- Hungry to learn: We are eager to see you learn new skills and grow.
- Team orientation: We work in small, fast-moving teams. We watch out for each other and go after big goals together as a team.
#LI-DNI

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Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/greenhouse%3Abaidu%3A3234325 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.