# Synthesis & STA Engineer – High-Speed SerDes at Astera

> United States · Unspecified · Software engineering · open. Source: https://alderhq.app/jobs/greenhouse%3Aasteralabs%3A4748148005 (read 2026-11-06).

## Facts (observed)

- Company: [Astera](https://alderhq.app/companies/astera)
- Location text: San Jose, California, United States; San Jose
- Where it can be done from (inferred): United States (evidence: "Location: San Jose, California, United States; San Jose")
- Posted: 2026-10-27 (10 days ago)
- First seen by alder: 2026-11-02 · last verified: 2026-11-04
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://job-boards.greenhouse.io/asteralabs/jobs/4748148005

## Pay and sponsorship

- Posted pay: not posted
- Market band for similar posted roles (SF Bay Area, n 1752): p25 $161k, median $200k, p75 $239k
- H-1B filings at this company for similar roles, FY26: 1 ([US DOL OFLC LCA disclosure data](https://www.dol.gov/agencies/eta/foreign-labor/performance))

## Description (the employer's text)

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

### About Astera Labs

Astera Labs is a global leader in purpose-built connectivity solutions for AI and cloud infrastructure. Our semiconductor-based platforms help solve signal, data, and memory connectivity bottlenecks in the world’s most demanding computing systems.

### Overview

As an Astera Labs Synthesis & STA Engineer – High-Speed SerDes you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of high-speed analog/mixed-signal SerDes and connectivity ASICs used in the world's leading cloud service providers, server, and network OEMs. This role requires end-to-end ownership of logic synthesis and static timing analysis across the digital portions of mixed-signal SerDes PHY designs, deep technical expertise in mixed-signal integration, and close collaboration with analog, RTL, physical design, and verification teams to ensure robust timing closure at advanced nodes.

### Key Responsibilities

- Perform RTL synthesis, driving area, power, and timing optimization for digital controller and DSP blocks within high-speed SerDes PHY designs.
- Author, develop, and validate SDC constraints from scratch, including clock definitions, generated clocks, multi-frequency/multi-mode constraints, I/O delays, false paths, multicycle paths, and clock-domain crossing exceptions unique to SerDes architectures.
- Set up and manage MMMC (Multi-Mode Multi-Corner) environments to enable accurate and efficient STA across process, voltage, and temperature (PVT) corners.
- Drive timing closure from synthesis through sign-off, ensuring robust timing across digital blocks embedded within analog/mixed-signal SerDes IP and full-chip SoC integration.
- Define and manage I/O timing budgets and interface constraints between analog and digital boundaries in hierarchical mixed-signal designs.
- Apply advanced sign-off methodologies at TSMC 5nm/3nm and below, including OCV/AOCV/POCV and PVT effects relevant to high-speed serial link performance.
- Leverage ETM/ILM libraries for hierarchical timing analysis and correlation of SerDes hard-macro blocks, balancing runtime and accuracy.
- Provide actionable timing feedback at both block and full-chip levels, including root cause analysis, timing debug, and ECO guidance for SerDes digital logic.
- Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage, developing scripts and flows to improve turnaround time.
- Generate and validate timing ECOs, partnering with physical design, analog, and RTL teams for quick closure on high-speed data-path and clock-path issues.
- Partner closely with analog/mixed-signal designers, SerDes architecture, implementation, and verification teams to drive timing convergence and provide sign-off level expertise for PHY-level and chip-level integration.
- Collaborate on clock tree and power domain strategies for SerDes digital blocks, ensuring compatibility with PLL/CDR-generated clocks and multi-supply domains.
### Basic Qualifications

- Bachelor's in Electrical Engineering or Computer Science required; Master's preferred.
- ≥8 years of experience in synthesis, timing constraints development, STA, and sign-off for high-speed mixed-signal IP in Server, Storage, Networking, or SerDes applications.

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Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/greenhouse%3Aasteralabs%3A4748148005 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.