# Principal Emulation Engineer at Astera

> United States · Principal · Software engineering · open. Source: https://alderhq.app/jobs/greenhouse%3Aasteralabs%3A4730620005 (read 2026-11-06).

## Facts (observed)

- Company: [Astera](https://alderhq.app/companies/astera)
- Location text: San Jose, California, United States; San Jose
- Where it can be done from (inferred): United States (evidence: "Location: San Jose, California, United States; San Jose")
- Posted: 2026-09-09 (58 days ago)
- First seen by alder: 2026-11-02 · last verified: 2026-11-04
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://job-boards.greenhouse.io/asteralabs/jobs/4730620005
- Skills listed (inferred): Python

## Pay and sponsorship

- Posted pay: not posted
- Market band for similar posted roles (SF Bay Area, n 195): p25 $226k, median $270k, p75 $320k
- H-1B filings at this company for similar roles, FY26: 1 ([US DOL OFLC LCA disclosure data](https://www.dol.gov/agencies/eta/foreign-labor/performance))

## Description (the employer's text)

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Principal Emulation Engineer — San Jose, CA

Role Overview

As a Principal Emulation Engineer, you will build and operate emulation environments that let verification teams stress-test complex ASICs before silicon. You’ll partner closely with design, verification, firmware, and systems engineers to model hardware-software interactions, exercise high-speed protocols, and isolate issues across RTL, transactors, test environments, and code. Your hands-on leadership will turn difficult debug problems into actionable fixes and improve confidence in each product milestone.

Astera Labs is accelerating the infrastructure behind AI by delivering purpose-built connectivity solutions for rack-scale systems. In this role, you’ll help validate the switching, PCIe, Ethernet, memory, and storage interfaces that connect the compute fabric—enabling faster bring-up, stronger interoperability, and more reliable platforms as the company scales.

Key Responsibilities

- Emulation and Prototyping
- Architect, build, and maintain emulation environments for complex ASICs and SoCs.
- Integrate RTL, transactors, protocol models, software, and test infrastructure to enable meaningful hardware-software co-simulation.
- Enable verification teams to stress-test designs with scalable, repeatable emulation workflows.
- Develop reusable models, utilities, and debug methodologies that accelerate pre-silicon validation.
- Protocol and SoC Verification
- Verify hardware-software interfaces and system behaviors in partnership with logic designers, firmware engineers, and verification teams.
- Exercise and debug PCI Express Gen 3 and above, Ethernet, DDR, NVMe, SPI, I2C/I3C, and similar interfaces.
- Analyze protocol behavior, functional coverage, performance, and corner cases across complex server, storage, and networking systems.
- Translate system requirements into practical emulation scenarios, tests, checkers, and measurable verification goals.
- Debug and Technical Leadership
- Debug design, environment, transactor, software, and test-code issues across the emulation stack.
- Identify software and hardware co-simulation limitations and apply effective isolation and debug techniques.
- Partner with cross-functional teams to prioritize a dynamic workload, resolve issues quickly, and drive risks to closure.
- Provide technical leadership, communicate clearly, and operate effectively with minimal guidance and supervision.
Basic Qualifications

- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- 8–12 years of experience supporting or developing complex SoC or silicon products for server, storage, or networking applications.
- Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs.
- Working knowledge of PCI Express Gen 3 or later, CXL, UALink, Ethernet, DDR, NVMe, SPI, I2C/I3C, or similar communication protocols.
- High proficiency in SystemVerilog and hardware verification environments.
- Experience understanding software and hardware co-simulation limitations and applying effective debug methods.
- Programming and scripting experience in Python, Perl, C, or similar languages.
- Professional, entrepreneurial, and open-minded approach with a can-do attitude, strong prioritization skills, and a customer-focused mindset.

---
Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/greenhouse%3Aasteralabs%3A4730620005 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.