# Lead Logic Design Engineer at Astera

> India · Staff · Software engineering · open. Source: https://alderhq.app/jobs/greenhouse%3Aasteralabs%3A4729060005 (read 2026-11-06).

## Facts (observed)

- Company: [Astera](https://alderhq.app/companies/astera)
- Location text: Bengaluru, Karnataka, India; Bengaluru
- Where it can be done from (inferred): India (evidence: "Location lists "bengaluru"")
- Posted: 2026-09-10 (57 days ago)
- First seen by alder: 2026-11-02 · last verified: 2026-11-04
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://job-boards.greenhouse.io/asteralabs/jobs/4729060005

## Pay and sponsorship

- Posted pay: not posted
- Market band for similar posted roles (Bengaluru, n 15): p25 ₹32.7L, median ₹42.5L, p75 ₹84.3L
- H-1B filings at this company for similar roles, FY26: 1 ([US DOL OFLC LCA disclosure data](https://www.dol.gov/agencies/eta/foreign-labor/performance))

## Description (the employer's text)

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Lead Logic Design Engineer – UALink IP/Subsystem

Experience

6–10 years

Job Summary

Lead RTL and microarchitecture development for UALink-based IP/subsystems, focusing on high-bandwidth, low-latency data movement and scalable interconnect design.

Key Responsibilities

- Lead UALink IP/subsystem RTL development.
- Translate protocol requirements into detailed microarchitecture.
- Design high-performance control and data-path logic.
- Work on buffering, arbitration, flow control, ordering, and error handling.
- Develop and review SystemVerilog RTL.
- Drive performance, area, power, and latency optimization.
- Collaborate with verification, SoC integration, and physical design teams.
- Debug complex functional and integration issues.
- Review RTL and mentor engineers.
- Support silicon debug and issue resolution.
Required Skills

- Strong RTL and microarchitecture experience.
- Experience with high-speed interconnects.
- Strong understanding of data movement, flow control, arbitration, and buffering.
- Excellent SystemVerilog/Verilog skills.
- Experience with CDC, lint, synthesis, and timing.
- Strong debugging and technical leadership skills.
Preferred

- Direct UALink experience.
- Experience with PCIe, CXL, CHI, CCIX, Ethernet, or similar technologies.
- Experience with AI/accelerator or high-performance compute SoCs.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/greenhouse%3Aasteralabs%3A4729060005 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.