# Senior Manager, Digital Design at Astera

> United States · Manager · Software engineering · open. Source: https://alderhq.app/jobs/greenhouse%3Aasteralabs%3A4727604005 (read 2026-11-07).

## Facts (observed)

- Company: [Astera](https://alderhq.app/companies/astera)
- Location text: San Jose, California, United States; San Jose
- Where it can be done from (inferred): United States (evidence: "Location: San Jose, California, United States; San Jose")
- Posted: 2026-09-17 (51 days ago)
- First seen by alder: 2026-11-02 · last verified: 2026-11-04
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://job-boards.greenhouse.io/asteralabs/jobs/4727604005

## Pay and sponsorship

- Posted pay: not posted
- Market band for similar posted roles (SF Bay Area, n 76): p25 $188k, median $226k, p75 $264k
- H-1B filings at this company for similar roles, FY26: 1 ([US DOL OFLC LCA disclosure data](https://www.dol.gov/agencies/eta/foreign-labor/performance))

## Description (the employer's text)

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

### Role Overview

As Senior Manager/Manager, Digital Design, you will lead the front-end digital design of high-performance PCIe & CXL, UAL, ethernet devices that enable reliable connectivity in rack-scale AI infrastructure. You will guide projects from requirements and architecture through RTL development, verification, physical design, tape-out, and product shipment, ensuring that complex designs meet demanding performance, quality, and schedule objectives.

This is an opportunity to influence the development of purpose-built connectivity products at a hyper-growth company, establish scalable design practices, and help deliver silicon that advances the next generation of AI systems.

### Key Responsibilities

### End-to-End Chip Development

- Lead digital design execution from product requirements and architecture through RTL, verification, tape-out, and production shipment.
- Drive delivery of at least two complex devices, maintaining clear milestones, technical decisions, risk tracking, and schedule accountability.
- Partner with architecture and system teams to translate PCIe & CXL, UAL, ethernet requirements into robust, scalable digital implementations.
### RTL Quality and Tape-Out Readiness

- Set expectations for high-quality front-end RTL that enables efficient synthesis, timing closure, physical implementation, and smooth tape-out.
- Establish and maintain design checklists, review gates, coding standards, and signoff criteria across the digital design lifecycle.
- Resolve design, performance, power, area, clocking, and integration issues in partnership with verification, physical design, DFT, and validation teams.
### Team and Cross-Functional Leadership

- Lead, mentor, and develop a team of 6–8 digital design engineers, fostering technical excellence, accountability, and effective collaboration.
- Influence cross-functional development decisions and align engineering teams around quality, risk reduction, and on-time execution.
- Communicate technical status, tradeoffs, dependencies, and mitigation plans to engineering and program leadership.
### Basic Qualifications

- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience with PCIe & CXL, UAL, ethernet digital design, including protocol implementation, high-speed connectivity requirements, and physical-layer considerations.
- 3-5 years of experience in engineering management or technical leadership in digital IC or ASIC design.
- Demonstrated ownership of chip design and development from requirements through tape-out and shipment for at least two devices of reasonable complexity.
- Strong hands-on expertise developing front-end RTL and applying design practices that support predictable physical design progress and tape-out quality.
- Ability to lead 6–8 engineers and influence execution across architecture, verification, physical design, DFT, firmware, validation, and operations.
### Preferred Qualifications

- Expertise in RTL quality methodologies, design reviews, lint, clock-domain and reset-domain considerations, synthesis, timing, and signoff readiness.
- Experience defining or improving design checklists, development flows, quality gates, and cross-functional tape-out processes.
- Building design blocks with large physical floorplan sizes is a plus

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