# Senior Principal ASIC Design Engineer at Astera

> Onsite · Germany · Principal · Software engineering · open. Source: https://alderhq.app/jobs/greenhouse%3Aasteralabs%3A4720467005 (read 2026-11-05).

## Facts (observed)

- Company: [Astera](https://alderhq.app/companies/astera)
- Location text: Germany (Onsite); Germany (Onsite)
- Where it can be done from (inferred): Onsite · Germany (evidence: "Location: Germany (Onsite); Germany (Onsite)")
- Posted: 2026-08-02 (95 days ago)
- First seen by alder: 2026-11-02 · last verified: 2026-11-04
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://job-boards.greenhouse.io/asteralabs/jobs/4720467005

## Pay and sponsorship

- Posted pay: not posted
- Market band for similar posted roles (Germany, n 116): p25 €64k, median €85k, p75 €123k
- H-1B filings at this company for similar roles, FY26: 1 ([US DOL OFLC LCA disclosure data](https://www.dol.gov/agencies/eta/foreign-labor/performance))

## Description (the employer's text)

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

### Senior Principal ASIC Design Engineer

Location: Germany (on-site)

### Role Overview

Astera Labs is building purpose-built silicon for rack-scale AI infrastructure. As a Distinguished Engineer, you will be a senior technical leader driving ASIC design for next-generation Ethernet and Scale-Up (ESUN) connectivity products.

You will set technical direction across the full ASIC design flow, spanning high-speed Ethernet, UALink, UCIe, and PCIe Gen 6/7. You will solve complex scale-up networking challenges, mentor senior engineers, and turn ambitious product goals into robust, manufacturable silicon.

### Technical Leadership & Architecture

- Define and drive ASIC architecture for Ethernet/ESUN connectivity products across UALink, UCIe, PCIe Gen 6/7, and Ethernet.
- Lead architecture and microarchitecture for high-performance Ethernet controllers, MACs, NIC datapaths, packet processing pipelines, and AI interconnect fabrics.
- Define scalable, low-latency, high-bandwidth data movement, scheduling, buffering, congestion management, QoS, reliability, and flow control.
- Architect hardware acceleration for NIC functions, RDMA, DMA, virtualization, and protocol offloads.
- Lead tradeoff analysis across performance, power, area, latency, scalability, resiliency, and programmability.
- Serve as a technical authority across digital, networking, and system domains.
### ASIC Design & Execution

- Lead RTL design and microarchitecture development for Ethernet controllers, MACs, NIC datapaths, protocol engines, and AI networking subsystems.
- Design packet processing architectures, DMA engines, queue management, scheduling, buffering, and memory subsystem interfaces.
- Develop hardware mechanisms for RDMA, zero-copy data movement, congestion control, transport reliability, and protocol acceleration.
- Design scalable architectures supporting virtualization, multi-tenant isolation, traffic management, and quality of service.
- Partner with firmware and software teams to define hardware/software interfaces for initialization, management, telemetry, performance monitoring, and diagnostics.
- Drive execution from architecture through RTL, integration, verification, tapeout, and post-silicon bring-up.
- Partner cross-functionally to meet performance, timing, power, area, manufacturability, and reliability targets.
### Basic Qualifications

- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 12+ years of ASIC/SoC design experience, with a track record of delivering complex, high-speed networking or connectivity silicon from architecture through production.
- Deep expertise in RTL design and microarchitecture for high-performance networking and connectivity ASICs.
- Extensive experience designing Ethernet controllers, MACs, NIC architectures, packet processing engines, or network interface subsystems.
- Strong understanding of RDMA architectures and transport protocols such as RoCE, InfiniBand concepts, or similar low-latency networking technologies.
- Experience designing hardware for packet parsing, scheduling, buffering, DMA, queue management, flow control, congestion management, and transport acceleration.
- Strong understanding of high-speed interconnects and protocols, including Ethernet, PCIe, and AI scale-up fabrics.
- Hands-on experience across the complete ASIC development flow, including architecture, RTL design, integration, synthesis, timing closure, physical implementation, tapeout, and post-silicon validation.

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Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/greenhouse%3Aasteralabs%3A4720467005 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.