# Hardware Lab Engineer at Astera

> United States · Unspecified · Software engineering · open. Source: https://alderhq.app/jobs/greenhouse%3Aasteralabs%3A4674439005 (read 2026-11-05).

## Facts (observed)

- Company: [Astera](https://alderhq.app/companies/astera)
- Location text: San Jose, California, United States; San Jose
- Where it can be done from (inferred): United States (evidence: "Location: San Jose, California, United States; San Jose")
- Posted: 2026-04-02 (217 days ago)
- First seen by alder: 2026-11-02 · last verified: 2026-11-04
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://job-boards.greenhouse.io/asteralabs/jobs/4674439005
- Skills listed (inferred): Python

## Pay and sponsorship

- Posted pay: $160k–$200k per year (from the description)
- Market band for similar posted roles (SF Bay Area, n 1495): p25 $161k, median $200k, p75 $247k
- H-1B filings at this company for similar roles, FY26: 1 ([US DOL OFLC LCA disclosure data](https://www.dol.gov/agencies/eta/foreign-labor/performance))

## Description (the employer's text)

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

### Overview

Astera Labs Inc. is seeking an experienced and self-driven Hardware Lab Engineer to join our dynamic team in developing world class connectivity products for AI infrastructure.

### Job Description

This role will work closely with firmware, system validation, quality, and product engineers to support silicon bring-up, characterization, and debug activities through hands-on lab execution. The ideal candidate will have a deep understanding of circuits, hands-on experience with PCBAs and silicon test environments, and the ability to work on complex, open-ended tasks with minimal oversight.

### Key Responsibilities

- Setup and maintain test environments for silicon validation and characterization. Configure and update hardware, software, firmware, and applications. Replicate BKCs.
- Conduct hands-on testing of silicon devices including PCIe Gen5/6/7, CXL, Ethernet, and other high-speed interfaces
- Install and configure servers, including FW, BIOS, OS, and network
- RMA intake/triage: inspection, electrical verification, screening (including CSAM inspection), and prioritization
- Manage logistics and communications with external labs
- Organize, track, and distribute lab equipment, hardware, and peripherals
- Ad hoc PCBA rework and soldering of fine-pitch SMD components
- Develop, document, and maintain lab procedures
### Required Qualifications

- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- 5-12+ years of hands-on experience in lab environments supporting silicon validation or hardware development
- Proficiency with high-speed test equipment (oscilloscopes, protocol analyzers, BERTs, multimeters)
- Experience with high-speed interface testing (PCIe, CXL, DDR, Ethernet, or SerDes)
- Strong programming skills in Python for test automation
- Familiarity with Linux operating systems and command-line tools
- Demonstrated experience coordinating with third-party testing laboratories and managing logistics, including sample shipping, chain of custody, and scheduling
- Strong organizational skills for managing multiple RMA cases simultaneously and prioritizing based on severity/impact
### Preferred Qualifications

- Experience with post-silicon validation of ASICs, SoCs, or Retimer/PHY products
- Knowledge of analog/mixed-signal circuit testing and debugging techniques
- Experience with JTAG, I2C, SPI, and other embedded interfaces
- Familiarity with PCB design, schematic reading, and signal integrity concepts
- Knowledge of data center systems architecture (servers, AI platforms, networking equipment)
- Understanding of ATE (Automated Test Equipment) systems and production test methodologies
- Experience with defect screening methodologies including visual inspection, electrical testing, and acoustic imaging
- Experience with complete RMA lifecycle management from intake through root cause analysis and corrective action
- Knowledge of common semiconductor failure modes and failure analysis techniques including die attach inspection, delamination detection, void analysis, and crack identification
- Experience with formal compliance testing and industry standards
The base salary range is $160,000.00 USD – $200,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

---
Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/greenhouse%3Aasteralabs%3A4674439005 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.