# Senior Principal Digital Design Engineer at Astera

> United States · Principal · Software engineering · open. Source: https://alderhq.app/jobs/greenhouse%3Aasteralabs%3A4672620005 (read 2026-11-05).

## Facts (observed)

- Company: [Astera](https://alderhq.app/companies/astera)
- Location text: San Jose, CA; San Jose
- Where it can be done from (inferred): United States (evidence: "Location: San Jose, CA; San Jose")
- Posted: 2026-03-12 (237 days ago)
- First seen by alder: 2026-11-02 · last verified: 2026-11-04
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://job-boards.greenhouse.io/asteralabs/jobs/4672620005

## Pay and sponsorship

- Posted pay: not posted
- Market band for similar posted roles (SF Bay Area, n 173): p25 $227k, median $270k, p75 $320k
- H-1B filings at this company for similar roles, FY26: 1 ([US DOL OFLC LCA disclosure data](https://www.dol.gov/agencies/eta/foreign-labor/performance))

## Description (the employer's text)

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

### Role Overview

Astera Labs is seeking a Senior Principal Digital Design Engineer to drive the architecture and implementation of next-generation digital designs powering AI infrastructure connectivity. This is a high-impact technical leadership role where you'll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

As a senior technical leader, you'll shape design methodologies, mentor engineering teams, and collaborate cross-functionally with verification, physical design, DFT, and post-silicon teams to deliver high-performance, production-quality silicon. You'll also influence roadmap decisions and drive design excellence across the organization, ensuring Astera Labs continues to set the standard for AI connectivity solutions.

### Key Responsibilities

### Architecture & Technical Leadership

- Define and drive micro-architecture for complex digital blocks and subsystems across multiple product lines
- Establish architectural standards and best practices that scale across the design organization
- Provide technical guidance and decision-making on critical design trade-offs impacting performance, power, and area
### Design Execution & Ownership

- Lead RTL implementation of complex designs from architecture definition through GDS and silicon bring-up
- Drive timing constraints and closure strategies and implement robust Design-for-Test (DFT) methodologies
- Own accountability for design quality, schedule, and successful production delivery
### Cross-Functional Collaboration

- Partner with verification teams to develop comprehensive test plans, achieve coverage closure, and debug complex issues
- Collaborate with physical design, DFT, and post-silicon teams to ensure seamless integration and bring-up
- Work with firmware and software teams to optimize hardware-software interfaces
### Mentorship & Process Excellence

- Mentor and develop junior and senior engineers, elevating team technical capabilities
- Drive continuous improvement of silicon development processes, CAD automation, and design infrastructure
- Contribute to organizational knowledge sharing and technical reviews
### Basic Qualifications

- Bachelor's degree in Electrical Engineering or equivalent
- 12+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
- Demonstrated expertise in architecture definition, micro-architecture development, RTL coding, synthesis, and timing closure
- Deep knowledge of at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
- Production experience with advanced CMOS nodes (≤7nm)
- Proficiency with Cadence and/or Synopsys digital design flows
- Track record of delivering multiple high-performance designs to production
### Preferred Qualifications

- Master's degree in Electrical Engineering or related field
- Experience with multiple high-speed protocols (PCIe Gen 5/6, CXL, UALink, Ethernet, DDR4/DDR5)
- Hands-on collaboration with embedded firmware teams and familiarity with RISC-V or Arm subsystems
- Proven contributions to design methodology, CAD automation, or infrastructure improvements

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Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/greenhouse%3Aasteralabs%3A4672620005 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.