# Digital Design Verification Engineer at OLIX

> Onsite · United Kingdom · Unspecified · Software engineering · open. Source: https://alderhq.app/jobs/ashby%3Aolix%3A2b552e68-0baf-493d-9c40-4e942fcb4d03 (read 2026-11-06).

## Facts (observed)

- Company: [OLIX](https://alderhq.app/companies/olix)
- Location text: Bristol, UK; Austin, TX
- Where it can be done from (inferred): Onsite · United Kingdom (evidence: "Location: Bristol, UK; Austin, TX")
- Posted: 2026-06-08 (151 days ago)
- First seen by alder: 2026-11-02 · last verified: 2026-11-04
- Reposted: 0 times · edited: 0 times
- Apply on the employer's site: https://jobs.ashbyhq.com/olix/2b552e68-0baf-493d-9c40-4e942fcb4d03
- Skills listed (inferred): Node.js, Python

## Pay and sponsorship

- Posted pay: £123k–£123k per year (from the listing's pay field)
- Market band for similar posted roles (Austin, n 122): p25 $140k, median $185k, p75 $214k

## Description (the employer's text)

### About OLIX

AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.

### The Role

We are seeking highly skilled and motivated Senior / Staff Digital Verification Engineers with a strong background in CMOS digital design and verification to take ownership of the functional correctness of high-speed, real-time data-processing silicon, from early algorithm modelling through verified RTL, sign-off, and silicon bring-up.

You will join a multidisciplinary group creating groundbreaking hardware where digital, optical, and mixed-signal domains intersect.

The ideal candidate brings deep expertise in digital verification methodologies, a solid understanding of hardware architecture, and a passion for building provably correct, high-performance systems that underpin breakthrough AI hardware.

### Responsibilities

Own end-to-end verification of high-throughput digital pipelines supporting multi-GSPS input rates, continuous streaming data paths, deep pipelining, and robust hand-shaking in advanced CMOS nodes

Develop and maintain comprehensive verification environments using SystemVerilog/UVM, including constrained-random testing, coverage closure, and regression automation

Define and implement assertion-based verification strategies for control logic, data-path correctness, CDC/RDC, and protocol compliance

Apply formal verification techniques (property checking, assertions, equivalence checking) to complement simulation-based verification and accelerate bug discovery

Model and validate algorithms using MATLAB/Simulink or Python, ensuring functional equivalence from algorithmic models through RTL and gate-level sign-off

Support FPGA prototyping and silicon bring-up by developing targeted testcases, debug strategies, and post-silicon validation plans

Collaborate closely with digital design, optical-hardware, mixed-signal, and software teams to ensure correct integration across clock domains, interfaces, and firmware abstractions

Analyse verification results to identify root causes, drive design fixes, and improve verification efficiency and reuse

Contribute to verification methodology development, documentation, and design/verification reviews; mentor junior engineers where appropriate

### Skills & Experience

5+ years of hands-on experience in digital verification for high-performance ASICs or SoCs

Ownership of verification for at least one complex block or subsystem processing continuous real-time data streams

Strong proficiency in SystemVerilog, assertions (SVA), and modern verification methodologies (e.g. UVM. CocoTB)

Proven experience verifying designs operating in GHz-class clock domains, including CDC/RDC analysis

Familiarity with industry-standard EDA flows: RTL simulation, formal verification, linting, CDC/RDC, STA, power-intent (UPF/CPF), and gate-level simulation

Experience verifying high-speed IP such as SerDes, DDR/HBM, PCIe, Ethernet, or similar interfaces

Proficiency with MATLAB/Simulink or Python/NumPy for algorithm modelling, fixed-point analysis, and test-vector generation

Solid grounding in digital design principles, computer architecture, DSP fundamentals, and semiconductor basics

Clear communicator who collaborates effectively across disciplines and is comfortable operating in a fast-moving, evolving environment

### Nice to have

Tape-out experience on an advanced process node

Deep hands-on experience with formal verification methodologies, including property decomposition, and coverage-driven formal on tools such as Jasper

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Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/ashby%3Aolix%3A2b552e68-0baf-493d-9c40-4e942fcb4d03 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.