# Physical Design Lead at Normal Computing

> Hybrid · United States · Staff · Design · open. Source: https://alderhq.app/jobs/ashby%3Anormalcomputing%3Aa68c2b6a-d1d4-4c6b-ac93-c8f0a600994b (read 2026-11-04).

## Facts (observed)

- Company: [Normal Computing](https://alderhq.app/companies/normal-computing)
- Location text: Mountain View; London; New York
- Where it can be done from (inferred): Hybrid · United States (evidence: "Location: Mountain View; London; New York")
- Posted: 2026-10-20 (14 days ago)
- First seen by alder: 2026-11-02 · last verified: 2026-11-04
- Reposted: 0 times · edited: 1 times
- Apply on the employer's site: https://jobs.ashbyhq.com/normalcomputing/a68c2b6a-d1d4-4c6b-ac93-c8f0a600994b

## Pay and sponsorship

- Posted pay: $200k–$400k per year (from the listing's pay field)
- Market band for similar posted roles (SF Bay Area, n 64): p25 $185k, median $213k, p75 $238k

## Description (the employer's text)

### Normal Computing \| Build with Us

Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), and London.

### The Role

Hybrid: 3 days a week in the office, in Mountain View, New York or London.

As the Physical Design Lead at Normal, you will lead the team that owns the end-to-end silicon realization path, taking complex architectures from synthesis and physical floorplanning all the way through timing signoff and GDSII tapeout. Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems, you will shape physical feasibility early in the design cycle by working shoulder-to-shoulder with RTL and architecture teams. You'll drive the full backend implementation flow—optimizing floorplanning, place-and-route (P&R), clock tree synthesis (CTS), static timing analysis (STA), and physical verification (DRC/LVS) to achieve aggressive power, performance, and area (PPA) targets.

We are looking for a seasoned engineer and lead who thrives in cross-functional environments and takes pride in tapeout-proven execution. The ideal candidate brings effective team building and leadership, a meticulous approach to physical signoff, maintains clarity in fast-paced build cycles, and is excited to solve the physical constraints of novel computing architectures.

### What You Will Own

Physical Design Team Hiring & Leadership: Provide leadership of the PD team, including necessary hiring to support the plan, and individual guidance and performance feedback

Project Planning: Create work estimates and schedule to support an aggressive tapeout plan

EDA tools acquisition: Specify and help negotiate the appropriate EDA tools to support the physical design methodology

Design & Floorplan Reviews: Collaborate closely with RTL, architecture, and DFT teams to influence early floorplanning, macro placement, pin assignments, and physical feasibility.

Physical Implementation & Flow: Lead the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and place-and-route (P&R).

Timing Closure & STA: Own static timing analysis (STA), timing constraints creation/validation, and signoff timing closure across all operating corners and modes.

Power, Area, and Signal Integrity: Drive physical optimization for power, performance, and area (PPA), as well as power integrity (IR/EM) and crosstalk analysis.

Physical Signoff & Verification: Execute full chip/block physical signoff checks, including DRC, LVS, ERC, and antenna fixes, ensuring seamless handoff to the foundry.

Tapeout & Post-Silicon Support: Create and execute tapeout checklists, manage final stream-out processes, and support post-silicon physical debugging and bring-up as needed.

### What Makes You a Great Fit

Tapeout Track Record: Lead at least 3+ successful tapeouts from netlist to signoff, ideally across advanced technology nodes.

PD Flow Expertise: Deep hands-on experience with industry-standard physical design tools (e.g., Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, Calibre) across floorplanning, P&R, CTS, and signoff timing closure.

Backend Debugging Instincts: Strong problem-solving skills in analyzing and resolving STA timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violations.

Cross-Functional Feasibility: Ability to collaborate effectively with RTL, architecture, and DFT teams to influence floorplanning, pin placement, and early physical feasibility.

Managerial experience: at least 7 years experience in role

### Bonus Points

Experience at an AI or high-performance compute (HPC) chip startup where design, verification, and PD work in tight iteration cycles.

Experience with custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging (e.g., chiplets, 2.5D/3D integration).

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Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/ashby%3Anormalcomputing%3Aa68c2b6a-d1d4-4c6b-ac93-c8f0a600994b and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.