# DFT Engineer at Delos Data > Remote · United States · Unspecified · Software engineering · open. Source: https://alderhq.app/jobs/ashby%3Adelos-data%3Ad2bf7cf1-382e-4073-935a-6c8037d37448 (read 2026-11-09). ## Facts (observed) - Company: [Delos Data](https://alderhq.app/companies/delos-data) - Location text: Palo Alto - Where it can be done from (inferred): Remote · United States (evidence: "Location: Palo Alto") - Posted: 2026-09-23 (47 days ago) - First seen by alder: 2026-11-04 · last verified: 2026-11-08 - Reposted: 0 times · edited: 0 times - Apply on the employer's site: https://jobs.ashbyhq.com/delos-data/d2bf7cf1-382e-4073-935a-6c8037d37448 - Skills listed (inferred): Python ## Pay and sponsorship - Posted pay: not posted - Market band for similar posted roles (SF Bay Area, n 1752): p25 $161k, median $200k, p75 $239k ## Description (the employer's text) ### DFT Engineer - Verification ### Who we are We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously. Some Recent Press: https://www.eetimes.com/startup-boosts-scale-up-to-1000-gpus-in-a-single-domain/ ### What we need A Senior DFT Verification Engineer responsible for ensuring the functionality, correctness, and quality of ASIC DFT logic. This role focuses on building robust verification environments, executing coverage-driven verification plans, and working closely with DFT design engineers and manufacturing engineers to deliver reliable, high-quality silicon. The ideal candidate has deep hands-on experience with SystemVerilog, UVM (or similar methodologies), and modern verification workflows, and is comfortable driving verification efforts from planning through closure. The ideal candidate is also knowledgeable about DFT topics such as scan/ATPG, JTAG, ijtag (ICL/PDL), boundary scan, MBIST, memory repair, and fuseboxes. Should have experience with gate-level simulation and tester pattern formats such as STIL. ### Key Responsibilities Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies Create and execute coverage-driven verification plans aligned with design specifications Use EDA DFT tools (e.g., TestMax, Tessent) to create and run recommended pre-silicon test cases for MBIST and scan fabric inserted by those tools Develop directed test cases for other (non-vendor-supplied) DFT logic to validate functionality and identify corner cases Assist in verifying ATPG patterns, especially at SOC level, along with manufacturing reset sequences Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis in collaboration with DFT design engineers Implement and track functional and code coverage, driving verification to closure Develop reusable verification components and write SystemVerilog Assertions (SVA) Participate in design and verification reviews, providing input on design testability, correctness, and optimization Automate regression testing and enhance verification infrastructure using Python and scripting Contribute to continuous improvement of verification processes, tools, and methodologies Along with the DFT designers, help support post-silicon test bring-up debug ### Required Skills and Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field 5+ years of experience in digital design verification, with at least 2 in DFT verification specifically Strong hands-on experience with UVM-based or similar verification methodologies Proficiency in SystemVerilog Experience in scripting (preferably Python) and automation Experience with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium) Experience with industry-standard EDA DFT tools (e.g., Synopsys TestMax + Yield Accelerator, Siemens Tessent) Solid understanding of digital design fundamentals Experience with verification of test sequences for high-speed PHY logic including PCIe and Ethernet (10G/40G/100G) Strong analytical and problem-solving skills Clear written and verbal communication skills for cross-functional collaboration High attention to detail and ability to deliver reliable, high-quality verification outcomes --- Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/ashby%3Adelos-data%3Ad2bf7cf1-382e-4073-935a-6c8037d37448 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.