# Staff Analog Design Engineer, SerDes Clocking at d-Matrix > Hybrid · United States · Staff · Software engineering · open. Source: https://alderhq.app/jobs/ashby%3Ad-Matrix%3A922e130d-e3b1-4923-afc9-b13d60c5c093 (read 2026-11-04). ## Facts (observed) - Company: [d-Matrix](https://alderhq.app/companies/d-matrix) - Location text: Santa Clara - Where it can be done from (inferred): Hybrid · United States (evidence: "Location: Santa Clara") - Posted: 2026-08-19 (78 days ago) - First seen by alder: 2026-11-02 · last verified: 2026-11-04 - Reposted: 0 times · edited: 0 times - Apply on the employer's site: https://jobs.ashbyhq.com/d-Matrix/922e130d-e3b1-4923-afc9-b13d60c5c093 - Skills listed (inferred): Python ## Pay and sponsorship - Posted pay: $155k–$250k per year (from the listing's pay field) - Market band for similar posted roles (SF Bay Area, n 851): p25 $206k, median $240k, p75 $281k - H-1B filings at this company for similar roles, FY26: 8, median offered wage $214k ([US DOL OFLC LCA disclosure data](https://www.dol.gov/agencies/eta/foreign-labor/performance)) ## Description (the employer's text) Join d-Matrix and help build the future of AI inference. We’ve pioneered a memory-centric architecture that brings compute directly into memory, making AI faster, more energy efficient, and accessible on a global scale. From chips and software to rack-scale systems, our team is tackling some of AI infrastructure’s hardest challenges — and shipping breakthrough technology today. If you want to create what comes next and help make infinite inference possible, we’d love to hear from you. Our culture is built on respect, collaboration, and direct communication. We value humility, we believe our different perspectives lead to better solutions, and we’re looking for people who are driven by execution and energized by hard problems. ### Role Overview This is a hands-on, transistor-level analog design role owning the clocking subsystem of d-Matrix's high-speed SerDes on our IO chiplet — including the PLL, DLL, phase interpolator, high-frequency clock distribution, and clock and data recovery (CDR) loop. This block set most often determines whether a link closes, and you will personally carry your designs from specification through silicon characterization. The work spans porting proven clocking blocks to new process nodes and ground-up design for our next-generation link, partnering closely with datapath, DSP, digital, and firmware teams to close timing, jitter budgets, and calibration across the full SerDes macro. ### What You Will Do Own transistor-level design of low-jitter frequency synthesis — LC and/or ring PLL, including loop filter, charge pump or digital loop, VCO, and divider chain. Own the phase interpolator and phase rotation scheme, including INL/DNL, glitch behavior, and interpolation resolution against the CDR's needs. Design high-frequency clock distribution across the SerDes macro: buffer chains, duty-cycle correction, quadrature generation and correction, skew control, and supply isolation. Define and verify CDR architecture and loop dynamics — bandwidth, jitter tolerance, jitter transfer, lock acquisition, and frequency offset tracking — modeling loop behavior in MATLAB, Python, or equivalent, and correlating against transistor-level and silicon results, in coordination with datapath and DSP owners. Build phase-noise and jitter budgets for the link and own the analysis showing where jitter originates. Build the verification environment for your blocks — PSS/HB and transient noise analysis, PVT corner coverage, Monte Carlo, and post-layout back-annotated simulation — and provide behavioral and Verilog-A models for full-chip verification. Drive layout of your blocks in deep sub-micron nodes, with particular attention to inductor and VCO layout, shielding, symmetry, and supply/substrate isolation. Take your blocks through silicon bring-up and bench characterization — phase noise, jitter tolerance, lock range — and correlate measured results against simulation. ### What You Will Bring BS/MS/PhD in Electrical Engineering, with 5+ years of hands-on analog and mixed-signal circuit design experience. Demonstrated ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon in a high-speed SerDes link. Deep knowledge of PLL architecture, loop dynamics, VCO design, and phase noise theory, along with working knowledge of CDR architectures and the loop analysis behind jitter tolerance and jitter transfer. Practical experience with jitter decomposition and budgeting methodology, including quantifying contributors in simulation. Circuit design experience in advanced FinFET or GAA process nodes, using industry-standard analog design and simulation tools and methodologies (e.g., Cadence Virtuoso, Spectre, Monte Carlo/corner analysis, post-layout simulation). Silicon bring-up and bench debug experience with lab equipment such as phase noise analyzers, high-speed scopes, and BERTs. ### Preferred Die-to-die interconnect experience — UCIe, BoW, or a proprietary D2D PHY — including clocking architecture choices specific to short-reach, low-energy-per-bit links. --- Data: alder (https://alderhq.app). Cite https://alderhq.app/jobs/ashby%3Ad-Matrix%3A922e130d-e3b1-4923-afc9-b13d60c5c093 and the date you read it. Observed facts come from the employer's own listing; location reach, level, family and skills are inferences.