Global · updated 15h ago
Celero Communications, Inc.
- Open roles
- 26
- Remote anywhere
- 0
can apply
- Top locations
- United States 17 · Canada 7 · Argentina 2
Observed by alder · through 7 Nov
Is Celero Communications, Inc. hiring?
Yes: Celero Communications, Inc. has 26 open roles on its own job board. 0 opened in the last 30 days. Most roles are United States, Canada, Argentina. Last change: 2026-11-07.
Hiring pulse
Hiring pulse · Learning · 2/7
Open rolesRemovedobserved
Open roles
DSP - FEC Design Engineer
Ottawa, Ontario, Canada and Vancouver, British Columbia, Canada; Ottawa, Canada; Vancouver, CanadaCAD 150k–250k7mo ago
Canada
Optical DSP Design Engineer
Ottawa, Ontario, Canada and Vancouver, British Columbia, Canada; Ottawa, Canada; Vancouver, CanadaCAD 150k–250k7mo ago
Canada
Post-Silicon Validation Engineer (Multiple Levels)
Irvine, CA, or Ottawa, Ontario, Canada; Irvine, CA; Ottawa, Canada17d ago
United States
Principal Analog Design Engineer
San Jose, CA; Irvine, CA; Ottawa, Canada; San Jose, CA; Vancouver, Canada$150k–250k8mo ago
United States
Principal Analog Design Engineer
Irvine, CA; Irvine, CA; Ottawa, Canada; San Jose, CA; Vancouver, Canada$150k–250k2mo ago
United States
Principal Analog Design Engineer
Ottawa, Ontario, Canada; Irvine, CA; Ottawa, Canada; San Jose, CA; Vancouver, Canada2mo ago
Canada
Principal Analog Design Engineer
Vancouver, British Columbia, Canada; Irvine, CA; Ottawa, Canada; San Jose, CA; Vancouver, Canada2mo ago
Canada
Principal Post-Silicon Validation Engineer
Irvine, CA, or San Jose, CA, or Ottawa, Ontario, Canada; Irvine, CA; Ottawa, Canada3mo ago
United States
| DSP - FEC Design Engineer DSP - FEC Design Engineer Celero Communications, Inc. · Ottawa, Ontario, Canada and Vancouver, British Columbia, Canada; Ottawa, Canada; Vancouver, Canada PythonC++ | CAD 150k–250k | 236d | Canada |
| High-Speed Analog Layout Design Engineer High-Speed Analog Layout Design Engineer Celero Communications, Inc. · Córdoba, Argentina; Irvine, CA Python | — | 47d | Argentina |
| Junior Emulation Engineer Junior Emulation Engineer Celero Communications, Inc. · Cordoba, Argentina; Córdoba, Argentina Python | — | 11d | Argentina |
| Marketing Director Marketing Director Celero Communications, Inc. · Irvine, CA; Irvine, CA | — | 109d | United States |
| Office Manager Office Manager Celero Communications, Inc. · San Jose, CA; San Jose, CA | — | 4d | United States |
| Optical DSP Design Engineer Optical DSP Design Engineer Celero Communications, Inc. · Ottawa, Ontario, Canada and Vancouver, British Columbia, Canada; Ottawa, Canada; Vancouver, Canada PythonC++ | CAD 150k–250k | 236d | Canada |
| Post-Silicon Validation Engineer (Multiple Levels) Post-Silicon Validation Engineer (Multiple Levels) Celero Communications, Inc. · Irvine, CA, or Ottawa, Ontario, Canada; Irvine, CA; Ottawa, Canada Python | — | 17d | United States |
| Principal Analog Design Engineer Principal Analog Design Engineer Celero Communications, Inc. · San Jose, CA; Irvine, CA; Ottawa, Canada; San Jose, CA; Vancouver, Canada | $150k–250k | 253d | United States |
| Principal Analog Design Engineer Principal Analog Design Engineer Celero Communications, Inc. · Irvine, CA; Irvine, CA; Ottawa, Canada; San Jose, CA; Vancouver, Canada | $150k–250k | 82d | United States |
| Principal Analog Design Engineer Principal Analog Design Engineer Celero Communications, Inc. · Ottawa, Ontario, Canada; Irvine, CA; Ottawa, Canada; San Jose, CA; Vancouver, Canada | — | 82d | Canada |
| Principal Analog Design Engineer Principal Analog Design Engineer Celero Communications, Inc. · Vancouver, British Columbia, Canada; Irvine, CA; Ottawa, Canada; San Jose, CA; Vancouver, Canada | — | 82d | Canada |
| Principal DFT Engineer Principal DFT Engineer Celero Communications, Inc. · Irvine, California, United States; Irvine, CA Node.jsPython | $200k–240k | 52d | United States |
| Principal High-Speed Analog Layout Design Engineer Principal High-Speed Analog Layout Design Engineer Celero Communications, Inc. · San Jose, CA; Irvine, CA Python | — | 47d | United States |
| Principal High-Speed Analog Layout Design Engineer Principal High-Speed Analog Layout Design Engineer Celero Communications, Inc. · Ottawa, Ontario, Canada; Irvine, CA Python | — | 47d | Canada |
| Principal High-Speed Analog Layout Design Engineer Principal High-Speed Analog Layout Design Engineer Celero Communications, Inc. · Irvine, CA; Irvine, CA Python | — | 47d | United States |
| Principal Optical Systems Engineer Principal Optical Systems Engineer Celero Communications, Inc. · Ottawa, Canada; Ottawa, Canada Python | — | 19d | Canada |
| Principal Physical Design Engineer Principal Physical Design Engineer Celero Communications, Inc. · Irvine, CA; Irvine, CA Python | $150k–250k | 47d | United States |
| Principal Physical Design Engineer Principal Physical Design Engineer Celero Communications, Inc. · San Jose, CA; Irvine, CA Python | $150k–250k | 47d | United States |
| Principal Physical Verification Engineer Principal Physical Verification Engineer Celero Communications, Inc. · San Jose, CA; San Jose, CA Python | $150k–250k | 47d | United States |
| Principal Physical Verification Engineer Principal Physical Verification Engineer Celero Communications, Inc. · Irvine, CA; San Jose, CA Python | $150k–250k | 47d | United States |
| Principal PLL Design Engineer Principal PLL Design Engineer Celero Communications, Inc. · Irvine, CA or San Jose, CA; Irvine, CA Node.js | $150k–250k | 215d | United States |
| Principal Post-Silicon Validation Engineer Principal Post-Silicon Validation Engineer Celero Communications, Inc. · Irvine, CA, or San Jose, CA, or Ottawa, Ontario, Canada; Irvine, CA; Ottawa, Canada Python | — | 100d | United States |
| Senior ASIC Design Engineer - DSP/Analog/SerDes Senior ASIC Design Engineer - DSP/Analog/SerDes Celero Communications, Inc. · San Jose, CA; San Jose, CA Python | — | 17d | United States |
| Senior ASIC Design Engineer - DSP/Analog/SerDes Senior ASIC Design Engineer - DSP/Analog/SerDes Celero Communications, Inc. · Irvine, CA; San Jose, CA Python | — | 17d | United States |
| Senior ASIC Design Engineer - DSP/Analog/SerDes Senior ASIC Design Engineer - DSP/Analog/SerDes Celero Communications, Inc. · Ottawa, Ontario, Canada; San Jose, CA Python | — | 17d | Canada |
| Sr. Principal Application Engineer Sr. Principal Application Engineer Celero Communications, Inc. · Irvine, CA, San Jose, CA; Irvine, CA PythonDistributed systems | — | 100d | United States |
Pay & sponsorship
observed
10 of 26 roles post pay
Software engineering, Principal · Los Angeles$200k–$200k n=5
Signals
observed
Roles usually close inClose time · Learning
Net roles · 7 daysVelocity · Learning
New team signalNew teams · Learning
Where they hire
United States17
Canada7
Argentina2